The present invention relates to integrated circuits and, more particularly, to integrated circuit assemblies with means for precisely aligning opposing integrated circuits.
Much of recent technological progress is derived from advances in integrated circuitry. Computers, scientific instruments and consumer electronics products generally contain large numbers of integrated circuit packages. Typically, an integrated circuit package includes an integrated circuit die and packaging which protects the die and interfaces the die to an incorporating system. The most salient advances in integrated circuit technology have been integrated circuits of increasing circuit density (e.g., very large scale integration (VLSI) circuits), functionality and complexity.
The advantages of increasing circuit density have included lower cost, in part due to the smaller number of parts required to assemble a system, and faster speeds, in part due to the fact that signals travel shorter distances within an integrated circuit than they travel between integrated circuits or discrete components. The cost advantages of VLSI technology can be offset as levels of integration increase. Highly integrated circuits are more subject to yield limitations, which increase the unit cost of working integrated circuits.
More significantly, highly integrated circuits are more difficult to test. Generally, chips are tested by contacting conductive "pads" on the chip using a test probe which is interfaced to a test instrument. The pads must be large enough to allow wire bonding, tape automated bonding, or solder bumps as well as allow reliable contact between the many contacts of the probe and respective pads on the chip during test. With simple integrated circuits, these pads can be distributed about the periphery of the chip. With more complex circuits, the required number of pads requires that they be distributed over the active surface of the chip. The size, distribution and number of pads limit circuit density. In addition, the pads add capacitance to signal paths, limiting the switching speed of the incorporating integrated circuit. Another disadvantage is that redesign of very complex circuits is exponentially more difficult and more frequently required than redesign of simple circuits.
Multi-chip packages have been designed which preserve most of the advantages of very complex single-chip packages while mitigating some significant disadvantages. In a multi-chip package, a complex circuit is distributed among two or more separate chips, each comprising a semiconductor substrate with circuit elements fabricated thereon. The circuitry on each chip can be relatively simple and therefore more easily tested and redesigned. The assembled chips can be included in a single package, maintaining the system manufacturing advantages enjoyed by single-chip packages. Electrical path distances can be made comparable to those in single-chip packages; in some cases, multi-chip packages provide shorter electrical paths.
Another advantage of multi-chip packages is the ease with which different processing technologies can be combined. For example, while bipolar and CMOS technologies have been implemented together on a single chip, the additional processing steps add to cost and reduce yield. A multi-chip package can include separate CMOS and bipolar chips so that there is no yield or process penalty in combining the technologies.
The challenge for multi-chip packages is the interfacing between the chips. Flip-chip interfacing is particularly attractive because it offers potential advantages over even single chip design in functional density. "Flip-chip" interfacing involves mating chips in opposing orientations so that their active surfaces are adjacent. Flip-chip interfacing minimizes electrical path lengths between chips and potentially doubles the circuit density available per unit area.
Demountable-chip multi-chip interfacing is also attractive because of the opportunities it affords for substitution testing. Normally, testing requires very expensive instruments with specially designed probes. However, in some cases a chip in a multi-chip package can be tested simply by installing it in a configuration of chips already known to work.
The key to successful implementation of the demountable-chip multi-chip approach is the conveniently repeatable precision alignment of chips. If the components cannot be aligned precisely, then large contact pads will be required. Large contact pads limit the circuit density of the chips and introduce capacitances which limit device speeds. If chip placement cannot be performed conveniently, repeatedly and precisely, substitution testing and component replacement will be much more difficult.
Typically, flip-chip assemblies utilize large contacts electrically connected using solder balls. These solder balls can be about 150 micrometers tall. Smaller amounts of solder could be used. However, these might fail to interface pads, which are subject to planar misalignment. Moreover, electrical contact can fail due to differential spacing between contacts due to lack of parallelism in the opposing surfaces of flip-chip interfaced chips. Furthermore, stress due to differential thermal expansion between opposing chips can cause the solder ball and its bonds with the chips to deteriorate; this deterioration can lead to electrical failure. What has not heretofore been provided is a system for the convenient, repeatable precision alignment and demountable contact of chips in a multi-chip arrangement. Preferably, the system should provide for reliable performance despite differential thermal expansion.